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november 2016 docid029956 rev 1 1 / 15 this is information on a product in full production. www.st.com STD4N90K5 n - channel 900 v, 1.90 typ.,3 a mdmesh? k5 power mosfet in a dpak package datasheet - production data figure 1 : internal schematic diagram features order code v ds r ds(on) max. i d STD4N90K5 900 v 2.10 3 a ? industrys lowest r ds(on) x area ? industrys best fom (figure of merit) ? ultra - low gate charge ? 100% avalanche tested ? zener - protected applications ? switching applications description this very high voltage n - channel power mosfet is designed using mdmesh? k5 technology based on an innovative proprietary vertical structure. the result is a dramatic r eduction in on - resistance and ultra - low gate charge for applications requiring superior power density and high efficiency. table 1: device summary order code marking package packing STD4N90K5 4n90k5 dpak tape and reel
contents STD4N90K5 2 / 15 docid029956 rev 1 contents 1 electrical ratings ................................ ................................ ............. 3 2 electrical characteristics ................................ ................................ 4 2.1 electrical characteri stics (curves) ................................ ...................... 6 3 test circuits ................................ ................................ ..................... 8 4 package information ................................ ................................ ....... 9 4.1 dpak package information ................................ ............................... 9 4.2 dpak packing informat ion ................................ .............................. 12 5 revision history ................................ ................................ ............ 14
STD4N90K5 electrical ratings docid029956 rev 1 3 / 15 1 electrical ratings table 2: absolute maximum ratings symbol parameter value unit v gs gate - source voltage 30 v i d drain current (continuous) at t c = 25 c 3 a i d drain current (continuous) at t c = 100 c 1.9 a i d (1) drain current (pulsed) 12 a p tot total dissipation at t c = 25 c 60 w dv/dt (2) peak diode recovery voltage slope 4.5 v/ns dv/dt (3) mosfet dv/dt ruggedness 50 t j operating junction temperature range - 55 to 150 c t stg storage temperature range notes: (1) pulse width limited by safe operating area (2) i sd 3 a, di/dt 100 a/s; v ds peak < v (br)dss , v dd = 450 v. (3) v ds 720 v table 3: thermal data symbol parameter value unit r thj - pcb (1) thermal resistance junction - pcb 50 c/w r thj - amb thermal resistance junction - ambient 62.5 c/w notes: (1) when mounted on fr - 4 board of 1 inch2, 2oz cu, t < 10 s. table 4: avalanche characteristics symbol parameter value unit i ar avalanche current, repetitive or not repetitive (pulse width limited by t jmax ) 1 a e as single pulse avalanche energy (starting t j = 25 c, i d = i ar , v dd = 50 v) 160 mj
electrical characteristics STD4N90K5 4 / 15 docid029956 rev 1 2 electrical characteristics t c = 25 c unless otherwise specified table 5: on/off - state symbol parameter test conditions min. typ. max. unit v (br)dss drain - source breakdown voltage v gs = 0 v, i d = 1 ma 900 v i dss zero gate voltage drain current v gs = 0 v, v ds = 900 v 1 a v gs = 0 v, v ds = 900 v t c = 125 c (1) 50 a i gss gate body leakage current v ds = 0 v, v gs = 20 v 10 a v gs(th) gate threshold voltage v dd = v gs , i d = 100 a 3 4 5 v r ds(on) static drain - source on - resistance v gs = 10 v, i d = 1.5 a 1.90 2.10 ? notes: (1) defined by design, not subject to production test. table 6: dynamic symbol parameter test conditions min. typ. max. unit c iss input capacitance v ds = 100 v, f = 1 mhz, v gs = 0 v - 173 - pf c oss output capacitance - 17.9 - pf c rss reverse transfer capacitance - 1 - pf c o(tr) (1) equivalent capacitance time related v ds = 0 to 720 v, v gs = 0 v - 29 - pf c o(er) (2) equivalent capacitance energy related - 11 - pf r g intrinsic gate resistance f = 1 mhz, i d = 0 a - 15.5 - ? q g total gate charge v dd = 720 v, i d = 3 a v gs = 10 v (see figure 15: "test circuit for gate charge behavior" ) - 5.3 - nc q gs gate - source charge - 1.45 - nc q gd gate - drain charge - 2.8 - nc notes: (1) time related is defined as a constant equivalent capacitance giving the same charging time as c oss when v ds increases from 0 to 80% v dss . (2) energy related is defined as a constant equivalent capacitance giving t he same stored energy as c oss when v ds increases from 0 to 80% v dss .
STD4N90K5 electrical characteristics docid029956 rev 1 5 / 15 table 7: switching times symbol parameter test conditions min. typ. max. unit t d(on) turn - on delay time v dd = 450 v, i d = 1.50 a, r g = 4.7 ? v gs = 10 v (see figure 14: "test circuit for resistive load switching times" and figure 19: "switching time waveform" ) - 10.5 - ns t r rise time - 11.8 - ns t d(off) turn - off delay time - 26.4 - ns t f fall time - 25.5 - ns table 8: source - drain diode symbol parameter test conditions min. typ. max. unit i sd source - drain current - 3 a i sdm (1) source - drain current (pulsed) - 12 a v sd (2) forward on voltage i sd = 3 a, v gs = 0 v - 1.5 v t rr reverse recovery time i sd = 3 a, di/dt = 100 a/s,v dd = 60 v (see figure 16: "test circuit for inductive load switching and diode recovery times" ) - 289 ns q rr reve rse recovery charge - 1.56 c i rrm reverse recovery current - 10.8 a t rr reverse recovery time i sd = 3 a, di/dt = 100 a/s v dd = 60 v, t j = 150 c (see figure 16: "test circuit for inductive load switching and diode recovery times" ) - 494 ns q rr reverse recovery charge - 2.45 c i rrm reverse recovery current - 9.9 a notes: (1) pulse width limited by safe operating area (2) pulsed: pulse duration = 300 s, duty cycle 1.5% table 9: gate - source zener diode symbol parameter test conditions min. typ. max. unit v (br)gso gate - source breakdown voltage i gs = 1 ma,i d = 0 a 30 - - v the built - in back - to - back zener diodes are specifically designed to enhance the esd performance of the device. the zener voltage facilitates efficient and cost - effective device integrity protection, thus eliminating the need for additional external componentry.
electrical characteristics STD4N90K5 6 / 15 docid029956 rev 1 2.1 electrical characteristics (curves) f igure 2 : safe operating area figure 3 : thermal impedance figure 4 : output characteristics figure 5 : transfer characteristics figure 6 : gate charge vs gate - source voltage figure 7 : static drain - source on - resistance k cg34360 c 10 -4 10 -3 10 -2 10 -1 t p (s) 10 -5 10 -1 10 -2 10 0
STD4N90K5 electrical characteristics docid029956 rev 1 7 / 15 figure 8 : capacitance variations figure 9 : normalized gate threshold voltage vs temperature figure 10 : normalized on - resistance vs temperature figure 11 : normalized v(br)dss vs temperature figure 12 : maximum avalanche energy vs starting tj figure 13 : source - drain diode forward characteristics
test circuits STD4N90K5 8 / 15 docid029956 rev 1 3 test circuits figure 14 : test circuit for resistive load switching times figure 15 : test circuit for gate charge behavior figure 16 : test circuit for inductive load switching and diode recovery times figure 17 : unclamped inductive load test circuit figure 18 : unclamped inductive waveform figure 19 : switching time waveform am01469v10 47 k 2.7 k 1 k i g = cons t 100 d.u. t . + pulse width v gs 2200 f v g v dd r l
STD4N90K5 p ackage information docid029956 rev 1 9 / 15 4 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and produ ct status are available at: www.st.com . ecopack ? is an st trademark. 4.1 dpak package information figure 20 : dpak (to - 252) type a package outli ne 0068772_a_21
package information STD4N90K5 10 / 15 docid029956 rev 1 table 10: dpak (to - 252) type a mechanical data dim. mm min. typ. max. a 2.20 2.40 a1 0.90 1.10 a2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 d 6.00 6.20 d1 4.95 5.10 5.25 e 6.40 6.60 e1 4.60 4.70 4.80 e 2.16 2.28 2.40 e1 4.40 4.60 h 9.35 10.10 l 1.00 1.50 (l1) 2.60 2.80 3.00 l2 0.65 0.80 0.95 l4 0.60 1.00 r 0.20 v2 0 8
STD4N90K5 package information docid029956 rev 1 11 / 15 figure 21 : dpak (to - 252) recommended footprint (dimensions are in mm)
package information STD4N90K5 12 / 15 docid029956 rev 1 4.2 dpak packing information figure 22 : dpak (to - 252) tape outline
STD4N90K5 package information docid029956 rev 1 13 / 15 figure 23 : dpak (to - 252) reel outline table 11: dpak (to - 252) tape and reel mechanical data tape reel dim. mm dim. mm min. max. min. max. a0 6.8 7 a 330 b0 10.4 10.6 b 1.5 b1 12.1 c 12.8 13.2 d 1.5 1.6 d 20.2 d1 1.5 g 16.4 18.4 e 1.65 1.85 n 50 f 7.4 7.6 t 22.4 k0 2.55 2.75 p0 3.9 4.1 base qty. 2500 p1 7.9 8.1 bulk qty. 2500 p2 1.9 2.1 r 40 t 0.25 0.35 w 15.7 16.3
revision history STD4N90K5 14 / 15 docid029956 rev 1 5 revision history table 12: document revision history date revision changes 02 - nov - 2016 1 first release.
STD4N90K5 docid029956 rev 1 15 / 15 important notice C please read carefully stmicroelectronics nv and its subsidiaries (st) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant information on st products before placing orders. st products are sold pursuant to sts terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and s t assumes no liability for application assistance or the design of purchasers products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information se t forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2016 stmicroelectronics C all rights reserved

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